(a) Field of the Invention
The present invention relates to a thin film transistor array panel and a manufacturing method thereof.
(b) Description of the Related Art
Liquid crystal displays (LCDs) are one of the most widely used flat panel displays. An LCD includes two panels provided with field-generating electrodes and a liquid crystal (LC) layer interposed therebetween. The LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the LC layer, which determines orientations of LC molecules in the LC layer to adjust polarization of incident light.
Among LCDs including field-generating electrodes on respective panels, a kind of LCDs provides a plurality of pixel electrodes arranged in a matrix at one panel and a common electrode covering an entire surface of the other panel. The image display of the LCD is accomplished by applying individual voltages to the respective pixel electrodes. For the application of the individual voltages, a plurality of three-terminal thin film transistors (TFTs) are connected to the respective pixel electrodes, and a plurality of gate lines transmitting signals for controlling the TFTs and a plurality of data lines transmitting voltages to be applied to the pixel electrodes are provided on the panel.
The panel for an LCD has a layered structure including several conductive layers and several insulating layers. The gate lines, the data lines, and the pixel electrodes are made from different conductive layers (referred to as “gate conductor,” “data conductor,” and “pixel conductor” hereinafter) preferably deposited in sequence and separated by insulating layers. A TFT includes three electrodes; a gate electrode made from the gate conductor and source and drain electrodes made from the data conductor. The source electrode and the drain electrode are connected by a semiconductor usually located thereunder, and the drain electrode is connected to the pixel electrode through a hole in an insulating layer.
In order to increase the aperture ratio, the pixel electrodes overlap adjacent signal lines such as the gate lines and the data lines and the parasitic capacitance between the pixel electrodes and the signal lines can be reduced by interposing a low dielectric organic insulator therebetween. The organic insulator is usually used along an inorganic insulator provided thereunder and the insulators have contact holes for connection between the drain electrodes and the pixel electrodes. The contact holes may have undercuts that the lower inorganic insulator is over-etched to the edges of the lower insulator is disposed under the upper insulator.
In the meantime, storage electrode lines are provided on the TFT array panel for forming storage capacitors along with the pixel electrodes. Although the storage capacitor can be increased by increasing overlapping area of the pixel electrodes and the storage electrode lines, it may decrease the aperture ratio.